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LM3S2739 Datasheet, PDF (59/532 Pages) List of Unclassifed Manufacturers – Microcontroller | |||
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LM3S2739 Microcontroller
6 System Control
6.1
6.1.1
6.1.2
6.1.2.1
6.1.2.2
6.1.2.3
System control determines the overall operation of the device. It provides information about the
device, controls the clocking to the core and individual peripherals, and handles reset detection and
reporting.
Functional Description
The System Control module provides the following capabilities:
â Device identification, see âDevice Identificationâ on page 59
â Local control, such as reset (see âReset Controlâ on page 59), power (see âPower
Controlâ on page 62) and clock control (see âClock Controlâ on page 62)
â System control (Run, Sleep, and Deep-Sleep modes), see âSystem Controlâ on page 64
Device Identification
Seven read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers.
Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
CMOD0 and CMOD1 Test-Mode Control Pins
Two pins, CMOD0 and CMOD1, are defined for use by Luminary Micro for testing the devices during
manufacture. They have no end-user function and should not be used. The CMOD pins should be
connected to ground.
Reset Sources
The controller has five sources of reset:
1. External reset input pin (RST) assertion, see âRST Pin Assertionâ on page 59.
2. Power-on reset (POR), see âPower-On Reset (POR)â on page 60.
3. Internal brown-out (BOR) detector, see âBrown-Out Reset (BOR)â on page 60.
4. Software-initiated reset (with the software reset registers), see âSoftware Resetâ on page 61.
5. A watchdog timer reset condition violation, see âWatchdog Timer Resetâ on page 61.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator.
RST Pin Assertion
The external reset pin (RST) resets the controller. This resets the core and all the peripherals except
the JTAG TAP controller (see âJTAG Interfaceâ on page 48). The external reset sequence is as
follows:
June 04, 2007
59
Preliminary
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