LM3S2739 Datasheet, PDF (158/532 Pages) List of Unclassifed Manufacturers – Microcontroller

General-Purpose Input/Outputs (GPIOs)
9.1.6
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
9.2 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 9-1 on page 158
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 9-2 on page 159 shows how a rising edge interrupt would be configured for pin
2 of a GPIO port.
Table 9-1. GPIO Pad Configuration Examples
Configuration
GPIO Register Bit Value^a
AFSEL
Digital Input (GPIO)
0
DIR
0
ODR
0
DEN
1
Digital Output (GPIO)
0
1
0
1
Open Drain Input
0
0
1
1
(GPIO)
Open Drain Output
0
1
1
1
(GPIO)
Open Drain
1
X
1
1
Input/Output (I²C)
Digital Input (Timer
1
X
0
1
CCP)
Digital Input (QEI)
1
X
0
1
Digital Output (PWM)
1
X
0
1
Digital Output (Timer
1
X
0
1
PWM)
Digital Input/Output
1
X
0
1
(SSI)
Digital Input/Output
1
X
0
1
(UART)
Analog Input
(Comparator)
0
0
0
0
Digital Output
(Comparator)
1
X
0
1
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
PUR
?
?
X
X
X
?
?
?
?
?
?
0
?
PDR
?
?
X
X
X
?
?
?
?
?
?
0
?
DR2R
X
?
X
?
?
X
X
?
?
?
?
X
?
DR4R
X
?
X
?
?
X
X
?
?
?
?
X
?
DR8R
X
?
X
?
?
X
X
?
?
?
?
X
?
SLR
X
?
X
?
?
X
X
?
?
?
?
X
?
158
June 04, 2007
Preliminary