NT5DS64M4AT Datasheet, PDF (7/78 Pages) List of Unclassifed Manufacturers – 256Mb Double Data Rate SDRAM

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Block Diagram (32Mb x 8)
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
13
15
13
A0-A12,
BA0, BA1
15
2
2
10 ^{Column-Address}
Counter/Latch
Bank3
Bank1 ^Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
(8192 x 512 x 16)
Sense Amplifiers
I/O Gating
DM Mask Logic
512
(x16)
Column
Decoder
9
COL0
1
16
16
16
Data
8
8
8
DQS
Generator
COL0 _Input
Register
Write ^{Mask 1}
1
FIFO
&
Drivers
1
2
16 ⁸
1
8
clk
out
clk
in
Data
8
8
1
DQS
1
8
CK,
COL0
CK
1
DQ0-DQ7,
DM
DQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
REV 1.1
12/2001
7
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