NT5DS64M4AT Datasheet, PDF (58/78 Pages) List of Unclassifed Manufacturers – 256Mb Double Data Rate SDRAM

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute Specifications
(0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
Symbol
Parameter
t_AC DQ output access time from CK/CK
t_DQSCK DQS output access time from CK/CK
t_CH CK high-level width
t_CL CK low-level width
t_CK
CL = 2.5
Clock cycle time
t_CK
CL = 2.0
t_DH DQ and DM input hold time
DDR266A
(-7K)
Min
− 0.75
Max
+ 0.75
− 0.75 + 0.75
0.45
0.55
0.45
0.55
7
12
7.5
12
10
12
0.5
DDR266B
(-75B)
Min
− 0.75
Max
+ 0.75
− 0.75 + 0.75
0.45
0.55
0.45
0.55
7.5
12
10
12
0.5
DDR200
(-8B)
Min
− 0.8
Max
+ 0.8
− 0.8
+ 0.8
0.45
0.55
0.45
0.55
8
12
Unit Notes
ns 1-4
ns 1-4
t_CK 1-4
t_CK 1-4
ns 1-4
10
12
ns 1-4
0.6
ns
1-4,
15,16
t_DS DQ and DM input setup time
0.5
0.5
0.6
ns
1-4,
15,16
t_DIPW DQ and DM input pulse width (each input)
t_HZ Data-out high-impedance time from CK/CK
t_LZ Data-out low-impedance time from CK/CK
t_DQSQ DQS-DQ skew (DQS & associated DQ signals)
t_DQSQA DQS-DQ skew (DQS & all DQ signals)
t_HP
minimum half clk period for any given cycle;
defined by clk high (t_CH) or clk low (t_CL) time
t_QH Data output hold time from DQS
1.75
− 0.75
− 0.75
t_CH
or
t_CL
t_HP-
0.75ns
+ 0.75
+ 0.75
+ 0.5
+ 0.5
1.75
− 0.75
− 0.75
t_CH
or
t_CL
t_HP-
0.75ns
+ 0.75
+ 0.75
+ 0.5
+ 0.5
2
− 0.8
− 0.8
t_CH
or
t_CL
+ 0.8
+ 0.8
+ 0.6
+ 0.6
t_HP-1.0ns
ns 1-4
ns 1-4, 5
ns 1-4, 5
ns 1-4
ns 1-4
t_CK 1-4
t_CK 1-4
t_DQSS
Write command to 1st DQS latching
transition
0.75
1.25
0.75
1.25
0.75
1.25 t_CK 1-4
t_DQSL,H DQS input low (high) pulse width (write cycle)
t_DSS DQS falling edge to CK setup time (write cycle)
t_DSH DQS falling edge hold time from CK (write cycle)
t_MRD Mode register set command cycle time
t_WPRES Write preamble setup time
t_WPST Write postamble
t_WPRE Write preamble
t_IH
Address and control input hold time
(fast slew rate)
0.35
0.2
0.2
14
0
0.40
0.25
0.9
0.60
0.35
0.2
0.2
15
0
0.40
0.25
0.9
0.60
0.35
0.2
0.2
16
0
0.40
0.25
1.1
0.60
t_CK 1-4
t_CK 1-4
t_CK 1-4
ns 1-4
ns 1-4, 7
t_CK 1-4, 6
t_CK 1-4
ns
2-4,
9,11,12
t_IS
Address and control input setup time
(fast slew rate)
0.9
0.9
1.1
ns
2-4,
9,11,12
t_IH
Address and control input hold time
(slow slew rate)
1.0
1.0
2-4,
1.1
ns 11,12,
14
t_IS
Address and control input setup time
(slow slew rate)
1.0
1.0
2-4,
1.1
ns 11,12,
14
REV 1.1
12/2001
58
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