NT5DS64M4AT Datasheet, PDF (60/78 Pages) List of Unclassifed Manufacturers – 256Mb Double Data Rate SDRAM

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Electrical Characteristics & AC Timing for DDR266 - Applicable Specifications
Expressed in Clock Cycles (0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
Parameter
t_MRD
t_WPRE
t_RAS
t_RC
t_RFC
t_RCD
t_RAP
t_RP
t_RRD
t_WR
t_DAL
t_WTR
t_XSNR
t_XSRD
Mode register set command cycle time
Write preamble
Active to Precharge command
Active to Active/Auto-refresh command period
Auto-refresh to Active/Auto-refresh
command period
Active to Read or Write delay
Active to Read Command with Autoprecharge
Precharge command period
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery + precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
t_CK = 7.5ns
Min
Max
2
0.25
6
16000
9
10
3
3
3
2
2
5
1
10
200
Units
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
Notes
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-5
1-4
1-4
1-4
1. Input slew rate = 1V/ns
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for sig-
nals other than CK/CK, is V_REF.
3. Inputs are not recognized as valid until V_REF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V_TT.
5. t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
REV 1.1
12/2001
60
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