NT5DS64M4AT Datasheet, PDF (46/78 Pages) List of Unclassifed Manufacturers – 256Mb Double Data Rate SDRAM

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Truth Table 2: Clock Enable (CKE)
1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. Command n is the command registered at clock edge n, and action n is a result of command n.
4. All states and sequences not shown are illegal or reserved.
Current State
Self Refresh
Self Refresh
Power Down
Power Down
All Banks Idle
All Banks Idle
Bank(s) Active
CKE n-1
Previous
Cycle
L
L
L
L
H
H
H
H
CKEn
Current
Cycle
Command n
Action n
L
X
Maintain Self-Refresh
H
Deselect or NOP
Exit Self-Refresh
L
X
Maintain Power-Down
H
Deselect or NOP
Exit Power-Down
L
Deselect or NOP
Precharge Power-Down Entry
L
Auto Refresh
Self Refresh Entry
L
Deselect or NOP
Active Power-Down Entry
See “Truth Table 3: Current State
H
Bank n - Command to Bank n (Same
Bank)” on page 47
Notes
1
1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t_XSNR) period. A minimum of
200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
REV 1.1
12/2001
46
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