NT5DS64M4AT Datasheet, PDF (57/78 Pages) List of Unclassifed Manufacturers – 256Mb Double Data Rate SDRAM

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
AC Input Operating Conditions (0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V, See AC
Characteristics)
Symbol
V_IH(AC)
V_IL(AC)
V_ID(AC)
V_IX(AC)
Parameter/Condition
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
Input Differential Voltage, CK and CK Inputs
Input Crossing Point Voltage, CK and CK Inputs
Min
Max
Unit
V_REF + 0.31
V
V_REF − 0.31
V
0.62
V_DDQ + 0.6
V
0.5*V_DDQ − 0.2 0.5*V_DDQ + 0.2 V
Notes
1, 2
1, 2
1, 2, 3
1, 2, 4
1. Input slew rate = 1V/ns.
2. Inputs are not recognized as valid until V_REF stabilizes.
3. V_ID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The value of V_IX is expected to equal 0.5*V_DDQ of the transmitting device and must track variations in the DC level of the same.
I_DD Specifications and Conditions (0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V, See AC
Characteristics)
Symbol
Parameter/Condition
I_DD0
I_DD1
I_DD2P
I_DD2N
I_DD3P
I_DD3N
I_DD4R
I_DD4W
I_DD5
I_DD6
I_DD7
Operating Current: one bank; active / precharge; t_RC = t_RC (min); DQ, DM, and
DQS inputs changing twice per clock cycle; address and control inputs changing
once per clock cycle
Operating Current: one bank; active / read / precharge; Burst = 2; t_RC = t_RC
(min); CL = 2.5; I_OUT = 0mA; address and control inputs changing once per clock
cycle
Precharge Power-Down Standby Current: all banks idle; power-down mode;
CKE ≤ V_IL (max)
Idle Standby Current: CS ≥ V_IH (min); all banks idle; CKE ≥ V_IH (min);
address and control inputs changing once per clock cycle
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ V_IL (max)
Active Standby Current: one bank; active / precharge; CS ≥ V_IH (min);
CKE ≥ V_IH (min); t_RC = t_RAS (max); DQ, DM, and DQS inputs changing twice per
clock cycle; address and control inputs changing once per clock cycle
Operating Current: one bank; Burst = 2; reads; continuous burst; address and
control inputs changing once per clock cycle; DQ and DQS outputs changing
twice per clock cycle; CL = 2.5; I_OUT = 0mA
Operating Current: one bank; Burst = 2; writes; continuous burst; address and
control inputs changing once per clock cycle; DQ and DQS inputs changing twice
per clock cycle; CL = 2.5
Auto-Refresh Current: t_RC = t_RFC (min)
Self-Refresh Current: CKE ≤ 0.2V
Operating current: four bank; four bank interleaving with BL = 4, address and
control inputs randomly changing; 50% of data changing at every transfer;
t RC = t RC (min); I OUT = 0mA.
DDR200
(8B)
t_CK=10ns
75
90
15
30
15
50
130
115
160
2
TBD
DDR266A/B
(7K/75B)
t_CK=7.5ns
Unit Notes
85
mA 1
110
mA 1
15
mA 1
35
mA 1
15
mA 1
60
mA 1
165
mA 1
150
170
2
TBD
mA 1
mA 1
mA 1, 2
mA 1
1. I_DD specifications are tested after the device is properly initialized.
2. Enables on-chip refresh and address counters.
REV 1.1
12/2001
57
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.