NT5DS64M4AT Datasheet, PDF (63/78 Pages) List of Unclassifed Manufacturers – 256Mb Double Data Rate SDRAM

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Data Input (Write) (Timing Burst Length = 4)
DQS
DQ
DM
t_DSL
t_DSH
t_DH
t_DS
DI n
t_DH
t_DS
DI n = Data In for column n.
3 subsequent elements of data in are applied in programmed order following DI n.
Don’t Care
Data Output (Read) (Timing Burst Length = 4)
CK
CK
t_HP
t_HP
t_HP
t_HP1
t_HP2
t_HP3
t_HP4
DQS
DQ
t_DQSQ
t_QH2
t_QH1
t_DQSQ
t_QH3
t_QH4
t_DQSQ
t_DQSQ
t_HP is the half cycle pulse width for each half cycle clock. t_HP is referenced to the clock duty cycle only
and not to the data strobe (DQS) duty cycle.
Data Output hold time from Data Strobe is shown as t_QH. t_QH is a function of the clock high or low time (t_HP)
for that given clock cycle. Note correlation of t_HP to t_QH in the diagram above (t_HP1 to t_QH1, etc.).
t_DQSQ (max)occurs when DQS is the earliest among DQS and DQ signals to transition.
REV 1.1
12/2001
63
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