NT5DS64M4AT Datasheet, PDF (13/78 Pages) List of Unclassifed Manufacturers – 256Mb Double Data Rate SDRAM

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions
include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (NTC
optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended
Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored informa-
tion until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are
idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these require-
ments result in unspecified operation.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to nor-
mal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when
entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled,
200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a Read command
can be issued. This is the reason for introducing timing parameter t_XSRD for DDR SDRAM’s (Exit Self Refresh to Read Com-
mand). Non- Read commands can be issued 2 clocks after the DLL is enabled via the EMRS command (t_MRD) or 10 clocks after
the DLL is enabled via self refresh exit command (t_XSNR, Exit Self Refresh to Non-Read Command).
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II.
QFC Enable/Disable
The QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system memory bus by
means of external FET switches when the given module (DIMM) is not being accessed. The QFC function is an optional feature
for NTC and is not included on all DDR SDRAM devices. Refer to the DDR SDRAM Device Labeling Table for proper differenti-
ation when ordering DDR devices with or without the QFC function. The QFC output is an open drain driver and must be con-
nected to V_DDQ through a pull up resistor at the board level if the QFC function is enabled. The recommended pull up resistance
is 150 ohms.
REV 1.1
12/2001
13
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