LM3S8971 Datasheet, PDF (543/577 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8971 Microcontroller
23.2.6
Table 23-20. External XTLP Oscillator Characteristics
Parameter Name Symbol Min Nom Max Unit
XTLN Input Low Voltage XTLN_ILV - - 0.8 -
XTLP Frequency^a XTLP_f - 25.0 - -
XTLP Period^b
T_clkper
- 40 -
-
XTLP Duty Cycle _XTLPDC 40 - 60 %
40
60
Rise/Fall Time
Absolute Jitter
T_r , T_f
- - 4.0 ns
- - 0.1 ns
a. IEEE 802.3 frequency tolerance ±50 ppm.
b. IEEE 802.3 frequency tolerance ±50 ppm.
Hibernation Module
The Hibernation Module requires special system implementation considerations since it is intended
to power-down all other sections of its host device. The system power-supply distribution and
interfaces of the system must be driven to 0 V_DC or powered down with the same regulator controlled
by HIB.
The regulators controlled by HIB are expected to have a settling time of 250 μs or less.
Table 23-21. Hibernation Module Characteristics
Parameter No Parameter
Parameter Name
Min Nom Max Unit
H1
t_{HIB_LOW} Internal 32.768 KHz clock reference rising edge to /HIB asserted - 200 - μs
H2
t_{HIB_HIGH} Internal 32.768 KHz clock reference rising edge to /HIB deasserted - 30 - μs
H3
t_{WAKE_ASSERT} /WAKE assertion time
62 - - μs
H4
t_WAKETOHIB /WAKE assert to /HIB desassert
H5
t_{XOSC_SETTLE} XOSC settling time^a
62 - 124 μs
20 - - ms
H6
t_{HIB_REG_WRITE} Time for a write to non-volatile registers in HIB module to complete 92 - - μs
H7
t_{HIB_TO_VDD} HIB deassert to VDD and VDD25 at minimum operational level
- - 250 μs
a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care
must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance).
Figure 23-3. Hibernation Module Timing
32.768 KHz
(internal)
H1
H2
/HIB
H4
/WAKE
H3
October 01, 2007
543
Preliminary