LM3S8971 Datasheet, PDF (304/577 Pages) List of Unclassifed Manufacturers – Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
1
0
Name
PE
FE
Type
RO
RO
Reset
0
0
Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
Write-Only Error Clear (UARTECR) Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DATA
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7:0
Name
reserved
DATA
Type
WO
WO
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
304
October 01, 2007
Preliminary