LM3S8971 Datasheet, PDF (455/577 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8971 Microcontroller
Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24),
address 0x18
This register enables software to control the behavior of the MDI/MDIX mux and its switching
capabilities.
Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24)
Base 0x4004.8000
Address 0x18
Type R/W, reset 0x00C0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PD_MODE AUTO_SW MDIX MDIX_CM
MDIX_SD
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
15:8
7
6
5
4
3:0
Name
reserved
PD_MODE
AUTO_SW
MDIX
MDIX_CM
MDIX_SD
Type
RO
R/W
R/W
R/W
RO
R/W
Reset
0x0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Parallel Detection Mode
When set, enables the Parallel Detection mode and allows auto-switching
to work when Auto-Negotiation is not enabled.
Auto-Switching Enable
When set, enables Auto-Switching of the MDI/MDIX mux.
Auto-Switching Configuration
When set, indicates that the MDI/MDIX mux is in the crossover (MDIX)
configuration.
When 0, it indicates that the mux is in the pass-through (MDI)
configuration.
When the AUTO_SW bit is 1, the MDIX bit is read-only. When the
AUTO_SW bit is 0, the MDIX bit is read/write and can be configured
manually.
Auto-Switching Complete
When set, indicates that the auto-switching sequence has completed.
If 0, it indicates that the sequence has not completed or that
auto-switching is disabled.
Auto-Switching Seed
This field provides the initial seed for the switching algorithm. This seed
directly affects the number of attempts [5,4] respectively to write bits
[3:0].
A 0 sets the seed to 0x5.
October 01, 2007
455
Preliminary