LM3S8971 Datasheet, PDF (110/577 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
reserved EPHY0 reserved EMAC0
Type RO
R/W
RO
R/W
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
reserved
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit/Field
31
30
29
28
27:8
Name
reserved
EPHY0
reserved
EMAC0
reserved
Type
RO
R/W
RO
R/W
RO
Reset
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
110
October 01, 2007
Preliminary