LM3S8971 Datasheet, PDF (17/577 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8971 Microcontroller
Synchronous Serial Interface (SSI) ............................................................................................ 334
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 346
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 348
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 350
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 351
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 353
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 354
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 356
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 357
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 358
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 359
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 360
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 361
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 362
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 363
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 364
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 365
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 366
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 367
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 368
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 369
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 370
Controller Area Network (CAN) Module ..................................................................................... 371
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 385
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 387
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 390
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 391
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 393
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 394
Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 396
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 397
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 397
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 398
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 398
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 401
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 401
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 402
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 402
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 403
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 403
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 404
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 404
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 405
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 405
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 407
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 407
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 407
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 407
October 01, 2007
17
Preliminary