LM3S8971 Datasheet, PDF (16/577 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 275
ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 276
ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 277
ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 278
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 279
ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 281
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 284
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 284
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 284
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 284
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 285
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 285
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 285
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 285
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 286
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 286
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 287
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 287
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 289
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 290
ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 291
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 293
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 301
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 303
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 305
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 307
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 308
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 309
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 310
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 312
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 314
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 316
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 318
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 319
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 320
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 322
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 323
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 324
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 325
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 326
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 327
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 328
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 329
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 330
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 331
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 332
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 333
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October 01, 2007
Preliminary