LM3S8971 Datasheet, PDF (18/577 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 407
CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 407
CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 407
CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 407
CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 408
CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 408
CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 409
CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 409
CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 410
CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 410
CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 411
CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 411
Ethernet Controller ...................................................................................................................... 412
Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 421
Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 423
Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 424
Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 425
Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 426
Register 6: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 427
Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 429
Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 430
Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 431
Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 432
Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 433
Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 434
Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 435
Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 436
Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 437
Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 438
Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 440
Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 442
Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 443
Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 444
Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 446
Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 447
Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 448
Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 450
Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 452
Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 453
Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 454
Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 455
Analog Comparator ..................................................................................................................... 456
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 460
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 461
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October 01, 2007
Preliminary