ISD-T360SB Datasheet, PDF (49/109 Pages) List of Unclassifed Manufacturers – VoiceDSP Digital Speech Processor with Master/Slave, Full-Duplex Speakerphone, Multiple Flash and ARAM/DRAM Support

2—SOFTWARE
ISD-T360SB
2.2.3 CODEC INTERFACE
SUPPORTED FUNCTIONALITY
The VoiceDSP processor supports analog and
digital telephony in various configurations. For
analog telephony the VoiceDSP operates in
master mode, where it provides the clock and
the synchronization signals. It supports a list of sin-
gle channel and dual channel codecs, as listed
in Table 1-7. For digital telephony the VoiceDSP
operates in slave mode, where the control sig-
nals are provided by an external source.
The codec interface is designed to exchange
data in short frame format as well as in long
frame format. The channel width may be either
8 bits (u-Law format or A-Law format), or 16 bits
(linear format). In slave mode the clock may be
divided by two, if required (two bit rate clock
mode).
The VoiceDSP support up to 2 voice channels,
where the line should be connected as channel
0 (in master mode or in slave mode - depends on
the configuration), and the speakerphone
(speaker and microphone) should be connect-
ed as channel 1 or as channel 2, depends on the
configuration (channel 1 and channel 2 are al-
ways connected as master).
See “The Codec Interface” on page 1-13, for de-
tailed description of the supported codec de-
vices and the hardware connectivity.
Use the CFG command to define the codec
mode (master or slave), the data frame format
(short or long), the channel width (8 bits or 16
bits), the clock bit rate (single or dual) and the
number and type of codecs (one or two, single
channel or dual channel). See “CFG Configure
VoiceDSP config_value” on page 2-25.
DATA CHANNELS TIMING
Especially in digital telephony, but also in analog
telephony when speakerphone is connected,
the channels data may be delayed from the
synchronization signal by variable number of
clock cycles. In order to allow full flexibility of the
data delay relative to the synchronization signal,
and the delay between the two synchronization
signals, a set of registers is provided. setting the
delay parameters of these registers defines the
exact timing of all the codec interface signals.
Refer to tunable parameters index 65 to index
69, in Table 2-11, for detailed description of the
delay registers and their significance.
2.3 ALGORITHM FEATURES
This section provides details of the VoiceDSP al-
gorithms and their principle operation. It is divid-
ed into the following subjects:
• VCD (Voice Compression and
Decompression)
• DTMF Detection
• Tone and Energy Detection (Call Progress)
• Speakerphone
• Speech Synthesis
ISD
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