ISD-T360SB Datasheet, PDF (46/109 Pages) List of Unclassifed Manufacturers – VoiceDSP Digital Speech Processor with Master/Slave, Full-Duplex Speakerphone, Multiple Flash and ARAM/DRAM Support

ISD-T360SB
2—SOFTWARE
INPUT SIGNALS
MWDIN
MICROWIRE Data In. Used for input only, for
transferring data from the microcontroller to the
VoiceDSP processor.
MWCLK
MICROWIRE Clock. Serves as the synchronization
clock during communication. One bit of data is
transferred on every clock cycle. The input data
is available on MWDIN and is latched on the
clock rising edge. The transmitted data is output
on MWDOUT on the clock falling edge. The sig-
nal should remain low when switching MWCS.
MWCS
MICROWIRE Chip Select. The MWCS signal is
cleared to 0, to indicate that the VoiceDSP pro-
cessor is being accessed. Setting MWCS to 1
causes the VoiceDSP processor to start driving
MWDOUT with bit 7 of the transmitted value. Set-
ting the MWCS signal resets the transfer-bit
counter of the protocol, so the signal can be
used to synchronize between the VoiceDSP pro-
cessor and the microcontroller.
To prevent false detection of access to the
VoiceDSP processor due to spikes on the MWCLK
signal, use this chip select signal, and toggle the
MWCLK input signal, only when the VoiceDSP
processor is accessed.
OUTPUT SIGNALS
MWDOUT
MICROWIRE Data Out. Used for output only, for
transferring data from the VoiceDSP processor to
the microcontroller. When the VoiceDSP proces-
sor receives data it is echoed back to the micro-
controller on this signal, unless the received data
is 0xAA. In this case, the VoiceDSP processor ech-
oes a command’s return value.
MWRDY
MICROWIRE Ready. When active (0), this signal
indicates that the VoiceDSP processor is ready to
transfer (receive or transmit) another byte of da-
ta.
This signal is set to 1 by the VoiceDSP processor
after each byte transfer has been completed. It
remains 1, while the VoiceDSP processor is busy
reading the byte, writing the next byte, or exe-
cuting the received command (after the last pa-
rameter has been received). MWRDY is cleared
to 0 after reset. For proper operation after a
hardware reset, this signal should be pulled up.
MWRQST
MICROWIRE Request. When active (0), this signal
indicates that new status information is avail-
able. MWRQST is deactivated (set to 1), after the
VoiceDSP processor receives a GSW (Get Status
Word) command from the microcontroller. After
reset, this signal is active (0) to indicate that a re-
set occurred. MWRQST, unlike all the signals of
the communication protocol, is an asynchro-
nous line that is controlled by the VoiceDSP firm-
ware.
SIGNAL USE IN THE INTERFACE PROTOCOL
After reset, both MWRQST and MWRDY are
cleared to 0.
The MWRQST signal is activated to indicate that
a reset occurred. The EV_RESET bit in the status
register is used to indicate a reset condition.
The GSW command should be issued after reset
to verify that the EV_RESET event occurred, and
to deactivate the MWRQST signal.
While the MWCS signal is active (0), the VoiceD-
SP processor reads data from MWDIN on every
rising edge of MWCLK. VoiceDSP processor also
writes every bit back to MWDOUT. This bit is either
the same bit which was read from MWDIN (in this
case it is written back as a synchronization echo
after some propagation delay), or it is a bit of a
value the VoiceDSP processor transmits to the
microcontroller (in this case it is written on every
falling edge of the clock).
2-6
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