ISD-T360SB Datasheet, PDF (22/109 Pages) List of Unclassifed Manufacturers – VoiceDSP Digital Speech Processor with Master/Slave, Full-Duplex Speakerphone, Multiple Flash and ARAM/DRAM Support

ISD-T360SB
1—HARDWARE
Figure 1-11: Codec Protocol-Short Frame—8-Bit Channel Width
Channel Width
The Codec interface supports both 8-bit and 16-
bit channel width in Master and Slave Modes.
Slave Mode
The VoiceDSP supports digital telephony appli-
cations including DECT and ISDN by providing a
Slave Mode of operation. In Slave Mode opera-
tion, the CCLK signal is input to the ISD-T360 and
controls the frequency of the codec interface
operation. The CCLK may take on any frequen-
cy between 500 KHz and 4 MHz. Both long and
short frame protocol are supported with only the
CFS1 output signal width affected. The CFS0 in-
put signal must be a minimum of one CCLK cy-
cle.
In slave mode, a double clock bit rate feature is
available as well. When the codec interface is
configured to double clock bit rate, the CCLK in-
put signal is divided internally by two and the re-
sulting clock used to control the frequency of the
codec of the codec interface operation.
This interface supports ISDN protocol with one bit
clock rate or double bit clock rate. The exact for-
mat is selected with the CFG command. The
slave codec interface uses four signals: CDIN,
CDOUT, CCLK, and CFS0. The CDIN, CCLK, and
CFS0 input pins and the CDOUT output pins are
connected to the ISDN/DECT agent. Data is
transferred to the VoiceDSP through the CDIN
pin and read out through the CDOUT pin. The
CFS0 pin is used to define the start of each frame
(see below) the source of that signal is at the
master side. The CCLK is used for bit timing of
CDIN and CDOUT. The rate of the CCLK is config-
ured via the CFG command and can be twice
of the data rate or at the data rate. The source
of that signal is at the master side.
1-14
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