ISD-T360SB Datasheet, PDF (33/109 Pages) List of Unclassifed Manufacturers – VoiceDSP Digital Speech Processor with Master/Slave, Full-Duplex Speakerphone, Multiple Flash and ARAM/DRAM Support

1—HARDWARE
1.3.5 TIMING DIAGRAMS
Figure 1-24: ROM Read Cycle Timing
ISD-T360SB
1. This cycle may be either TI (Idle), T3 or T3H.
2. Data can be driven by an external device at T2W1, T2W, T2 and T3.
3. This cycle may be either TI (Idle) or T1.
Figure 1-25: ARAM/DRAM Refresh Cycle Timing (Normal Operation)
1. This cycle may be either TI (Idle) or T1 of any non-DRAM bus cycle. If the next bus cycle is a DRAM one, T3RF is
followed by three TI (Idle) cycles.
ISD
1-25