ISD-T360SB Datasheet, PDF (34/109 Pages) List of Unclassifed Manufacturers – VoiceDSP Digital Speech Processor with Master/Slave, Full-Duplex Speakerphone, Multiple Flash and ARAM/DRAM Support

ISD-T360SB
1—HARDWARE
Figure 1-26: ARAM/DRAM Power-Down Refresh Cycle Timing
Figure 1-27: DRAM Read Cycle Timing
TI
T1 T2W1 T2W2 T2W3 6xT2W T2 T3
TI
TI
TI T1 T2W1 T2W2 T2W3
(Note 2)
CTTL
RAS
t_RASa
t_RASh
t_RASia
t_RASh
CAS
t_CASa
t_CASh
t_CASia
t_CASh
A0-10
or
A0-15
(Note 1) _tAv
DWE
D0-1,
D3-7
t_Df
Row
t_Av
t_Ah
Column
t_Ah
(Note 3)
Data In
t_DIs t_DIh
(Note 3)
D2/RA11
RA11
D2 In
RA11
t_Df
t_Av
t_Df
t_DIs t_DIh
1. A0-A10 in the IRE environment, when Expansion
Memory is disabled; otherwise A0-A15.
2. This cycle may be either TI (Idle) or T1 of any non-DRAM bus cycle. If the next bus cycle is to DRAM, T3 is followed by
three TI (Idle) cycles.
3. An external device can drive data from T2W3 to T3.
1-26
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