DS89C420 Datasheet, PDF (7/59 Pages) Dallas Semiconductor – Ultra-High-Speed Microcontroller

DS89C420
Compatibility
The DS89C420 is a fully static CMOS 8051-compatible microcontroller similar to the DS87C520 in
functional features, but with much higher performance. In most cases the DS89C420 can drop into an
existing socket for the 8xC51 family to improve the operation significantly. While remaining familiar to
8051 family users, it has many new features. The DS89C420 runs the standard 8051 family instruction set
and is pin compatible with DIP, PLCC, and TQFP packages. In general, software written for existing
8051-based systems works without DS89C420 modification, with the exception of critical timing
routines, since the DS89C420 performs its instructions much faster than the original for any given crystal
selection.
The DS89C420 provides three 16-bit timer/counters, two full-duplex serial ports, and 256 bytes of direct
RAM plus 1kB of extra MOVX RAM. I/O ports can operate as in standard 8051 products. Timers default
to a 12 clock-per-cycle operation to keep their timing compatible with original 8051 family systems.
However, timers are individually programmable to run at the new 1 clock-per-cycle if desired. The
DS89C420 provides several new hardware features implemented by new SFRs.
Performance Overview
The DS89C420 features a completely redesigned high-speed 8051-compatible core and allows operation
at a higher clock frequency, but the updated core does not have the dummy memory cycles that are
present in a standard 8051. A conventional 8051 generates machine cycles using the clock frequency
divided by 12. In the DS89C420, the same machine cycle takes 1 clock. Thus, the fastest instructions
execute 12 times faster for the same crystal frequency (and actually 24 times faster for the INC data
pointer instruction). It should be noted that this speed improvement reduces when using external memory
access modes that require more than 1 clock per cycle.
Improvement of individual programs depends on the actual instructions used. Speed-sensitive
applications make the most use of instructions that are 12 times faster. However, the sheer number of 12-
to-1 improved op codes makes dramatic speed improvements likely for any code. These architecture
improvements produce instruction cycle times as low as 30ns (33MIPs). The dual data pointer feature
also allows the user to eliminate wasted instructions when moving blocks of memory. The new page
modes allow for increased efficiency in external memory accesses.
Instruction Set Summary
All instructions perform the same functions as their 8051 counterparts. Their effect on bits, flags, and
other status functions is also identical. However, the timing of each instruction is different in both
absolute and relative number of clocks.
For absolute timing of real-time events, the timing of software loops can be calculated using information
in the “Instruction Set” table of the Ultra-High-Speed Flash Microcontroller User’s Guide. However,
counter/timers default to run at the older 12 clocks per increment. In this way, timer-based events occur at
the standard intervals with software executing at higher speed. Timers optionally can run at lower
numbers of clocks per increment to take advantage of faster processor operation.
The relative time of some instructions might be different in the new architecture than it was previously.
For example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct,
direct” instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same
amount of time. In the DS89C420, the MOVX instruction takes as little as two machine cycles or two
oscillator cycles but the “MOV direct, direct” uses three machine cycles or three oscillator cycles. While
both are faster than their original counterparts, they now have different execution times. This is because
the DS89C420 usually uses one machine cycle for each instruction byte and requires one cycle for
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