DS89C420 Datasheet, PDF (22/59 Pages) Dallas Semiconductor – Ultra-High-Speed Microcontroller

DS89C420
External Memory
The DS89C420 executes external memory cycles for code fetches and read/writes of external program
and data memory. A non-page external memory cycle is four times slower than the internal memory
cycles (i.e., an external memory cycle contains four system clocks)*. However, a page mode external
memory cycle can be completed in 1, 2, or 4 system clocks for a page hit and 2, 4, or 8 system clocks for
a page miss, depending on user selection. The DS89C420 also supports a second page mode operation
with a different external bus structure that provides for fast external code fetches but uses 4 system clock
cycles for data memory access.
*For this reason, although a DS89C420 can be substituted for a ROM-less 8051 device (DS80C310,
C320, etc.), there is no increase in execution speed.
External Program Memory Interface (Non-Page Mode)
Figure 4 shows the timing relationship for internal and external code fetches when CD1 and CD0 are set
to 10b, assuming the microcontroller is in non-page mode for external fetches. Note that an external
program fetch takes 4 system clocks, and an internal program fetch requires only 1 system clock.
As illustrated in Figure 4, ALE is deasserted when executing an internal memory fetch. The DS89C420
provides a programmable user option to turn on ALE during internal program memory operation. ALE is
automatically enabled for code fetch externally, independent of the setting of this option.
PSEN is only asserted for external code fetches, and is inactive during internal execution.
Figure 4. External Program Memory Access (Non-Page Mode and
CD1:CD0 = 10)
Internal Memory Cycles
XTAL1
Ext Memory Cycle
C1 C2 C3 C4
Ext Memory Cycle
C1 C2 C3 C4
ALE
PSEN
Port 0
LSB Add
Data LSB Add
Data
Port 2
MSB Add
MSB Add
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