DS89C420 Datasheet, PDF (38/59 Pages) Dallas Semiconductor – Ultra-High-Speed Microcontroller

DS89C420
the multiplier startup counter. During the multiplier startup period the CKRY bit remains cleared and the
CD1 and CD0 clock controls cannot be set to 00b. The CTM bit is cleared to a logic 0 on all resets.
Figure 11 gives a simplified diagram of the generation of the system clocks. Specifics of hardware
restrictions associated with the use of the 4X/ 2X CTM, CKRY, CD1, and CD0 bits are outlined in the
SFR description.
Figure 11. System Clock Sources
Crystal
Oscillator
4X/2X
CTM
Clock
Multiplier
Ring
Enable
Divide 1024
Ring
Oscillator
CD0
CD1
MUX
Selector
System
Clock
Bandgap-Monitored Interrupt and Reset Generation
The power monitor in the DS89C420 monitors the V_CC pin in relation to the on-chip bandgap voltage
reference. Whenever V_CC falls below V_PFW, an interrupt is generated if the corresponding power-fail
interrupt-enable bit EPFI (WDCON.5) is set, causing the device to vector to address 33h. The power-fail
interrupt-status bit PFI (WDCON.4) is set anytime V_CC transitions below V_PFW, and can only be cleared
by software once set. Similarly, as V_CC falls below V_RST, a reset is issued internally to halt program
execution. Following power-up, a power-on reset initiates a power-on reset timeout before starting
program execution. When V_CC is first applied to the DS89C420, the processor is held in reset until
V_CC > V_RST and a delay of 65,536 oscillator cycles has elapsed, to ensure that power is within tolerance
and the clock source has had time to stabilize. Once the reset timeout period has elapsed, the reset
condition is removed automatically and software execution begins at the reset vector location of 0000h.
The power-on reset flag POR (WDCON.6) is set to logic 1 to indicate a power-on reset has occurred, and
can only be cleared by software.
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