DS89C420 Datasheet, PDF (4/59 Pages) Dallas Semiconductor – Ultra-High-Speed Microcontroller

DS89C420
Table 1. Pin Description
PIN
NAME
DIP
PLCC TQFP
40
12, 44 6, 38
V_CC
V_CC - +5V
FUNCTION
20
1, 22, 23, 16, 17,
34
28, 39
GND GND. Logic Ground
9
10
4
RST _{External Reset. The RST input pin is bidirectional and contains}
a Schmitt trigger to recognize external active-high reset inputs.
The pin also employs an internal pulldown resistor to allow for a
combination of wire OR’d external reset sources. An RC is not
required for power-up, since the device provides this function
internally.
19
21
15
XTAL1 _{XTAL1, XTAL2. The crystal oscillator pins XTAL1 and}
18
20
14
XTAL2 XTAL2 provide support for fundamental mode parallel resonant,
AT cut crystals. XTAL1 also acts as an input if there is an
external clock source in place of a crystal. XTAL2 serves as the
output of the crystal amplifier.
29
32
26
PSEN Program Store Enable. This signal is commonly connected to
optional external program memory as a chip enable. PSEN
provides an active-low pulse and is driven high when external
program memory is not being accessed. In 1-cycle page mode 1,
PSEN remains low for consecutive page hits.
30
33
27 _{ALE/ PROG Address Latch Enable. Functions as a clock to latch the}
external address LSB from the multiplexed address/data bus on
Port 0. This signal is commonly connected to the latch enable of
an external 373 family transparent latch. In default mode, ALE
has a pulse width of 1.5 XTAL1 cycles and a period of four
XTAL1 cycles. In page mode, the ALE pulse width is altered
according to the page mode selection. In traditional 8051 mode,
ALE is high when using the EMI reduction mode and during a
reset condition. ALE can be enabled by writing ALEON = 1
(PMR.2). Note that ALE operates independently of ALEON
during external memory accesses. As an alternate mode, this pin
( PROG ) is used to execute the parallel program function.
39
43
37 P0.0 (AD0) Port 0 (AD0–7), I/O. Port 0 is an open-drain 8-bit, bidirectional
38
42
36 P0.1 (AD1) ^{I/O port. As an alternate function, Port 0 can function as the}
37
41
35
P0.2 (AD2)
multiplexed address/data bus to access off-chip memory. During
the time when ALE is high, the LSB of a memory address is
36
40
34 P0.3 (AD3) _{presented. When ALE falls to a logic 0, the port transitions to a}
35
39
33 P0.4 (AD4) bidirectional data bus. This bus is used to read external program
34
38
32 P0.5 (AD5) ^{memory and read/write external RAM or peripherals. When}
33
37
31 P0.6 (AD6) ^{used as a memory bus, the port provides weak pullups for logic}
32
36
30
P0.7 (AD7)
1 outputs. The reset condition of Port 0 is three-state. Pullup
resistors are required when using Port 0 as an I/O port.
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