DS89C420 Datasheet, PDF (36/59 Pages) Dallas Semiconductor – Ultra-High-Speed Microcontroller

DS89C420
Timed Access
The timed access function provides control verification to system functions. The timed access function
prevents an errant CPU from making accidental changes to certain SFR bits that are considered vital to
proper system operation. This is achieved by using software control when accessing the following SFR
control bits:
WDCON.0
WDCON.1
WDCON.3
WDCON.6
EXIF.0
ACON.5
ACON.6
ACON.7
ROMSIZE.0
ROMSIZE.1
ROMSIZE.2
ROMSIZE.3
FCNTL.0
FCNTL.1
FCNTL.2
FCNTL.3
RWT
EWT
WDIF
POR
BGS
PAGES0
PAGES1
PAGEE
RMS0
RMS1
RMS2
PRAME
FC0
FC1
FC2
FC3
Reset Watchdog Timer
Watchdog Reset Enable
Watchdog Interrupt Flag
Power-On Reset Flag
Bandgap Select
Page Mode Select Bit 0
Page Mode Select Bit 1
Page Mode Enable
Program Memory Size Select Bit 0
Program Memory Size Select Bit 1
Program Memory Size Select Bit 2
Program RAM Enable
Flash Command Bit 0
Flash Command Bit 1
Flash Command Bit 2
Flash Command Bit 3
Before these bits can be altered, the processor must execute the timed access sequence. This sequence
consists of writing an AAh to the timed access (TA, C7h) register, followed by writing a 55h to the same
register within three machine cycles. This timed sequence of steps then allows any of the timed access-
protected SFR bits to be altered during the three machine cycles, following the writing of the 55h.
Writing to a timed access-protected bit outside of these three machine cycles has no effect on the bit.
The timed access process is address-, data-, and time-dependent. A processor running out of control and
not executing system software cannot statistically perform this timed sequence of steps, and as such, will
not accidentally alter the protected bits. It should be noted that this method should be used in the main
body of the system software and never used in an interrupt routine in conjunction with the watchdog
reset. Interrupt routines using the timed-access watchdog-reset bit (RWT) can recover a lost system and
allow the resetting of the watchdog, but the system returns to a lost condition once the RETI is executed,
unless the stack is modified. It is advisable that interrupts be disabled (EA = 0) when executing the timed
access sequence, since an interrupt during the sequence adds time, making the timed access attempt fail.
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