DS89C420 Datasheet, PDF (49/59 Pages) Dallas Semiconductor – Ultra-High-Speed Microcontroller

DS89C420
Note 1: The system clock frequency is dependent on the oscillator frequency and the setting of the clock-divide control bits (CD1 and CD0) and the crystal
multiplier control bits (4X/ 2X and CTM) in the PMR register. The term “1 / tCLCL” used in the variable timing table is calculated through the use
of the table given below.
4X/ 2X
CD1
1
0
0
0
X
0
X
1
X
1
CD0
0
0
1
0
1
NUMBER OF OSCILLATOR CYCLES
PER SYSTEM CLOCK (1 / tCLCL)
4 Oscillator Cycles
2 Oscillator Cycles
Reserved
1 Oscillator Cycle
1 / 1024 Oscillator Cycle
Note 2: External MOVX instruction times are dependent on the setting of the MD2, MD1, and MD0 bits in the clock control register. The terms
“tSTC1, tSTC2, tSTC3” used in the variable timing table are calculated through the use of the table given below.
MD2
0
0
0
0
1
1
1
1
MD1
0
0
1
1
0
0
1
1
MD0
0
1
0
1
0
1
0
1
MOVX INSTRUCTION TIME
(MACHINE CYCLES)
2
3
4
5
9
10
11
12
tSTC1
(tCLCL)
0
2
6
10
14
18
22
26
tSTC2
(tCLCL)
0
1
1
1
5
5
5
5
tSTC3
(tCLCL)
0
0
0
0
4
4
4
4
tSTC4
(tCLCL)
0
0
0
0
1
1
1
1
tSTC5
(tCLCL)
0
1
1
1
1
1
1
1
Note 3: Maximum load capacitance (to meet the above timing) for Port 0, ALE, PSEN , WR , and RD is limited to 60pF. Port 1, 2, 3, and 4
(except for P3.6, WR and P3.7, RD ) are tested with a capacitance of 50pF. XTAL1 and XTAL2 load capacitance is dependent on
the frequency of the selected crystal.
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