DS89C420 Datasheet, PDF (32/59 Pages) Dallas Semiconductor – Ultra-High-Speed Microcontroller

DS89C420
Figure 10. Page Mode 1, External Data Memory Access (Pages = 01,
Stretch = 4, CD = 10)
XTAL1
1st
Cycle
2nd
Cycle
MOVX Instruction (Page miss)
3rd
Cycle
4th
Cycle
9th
Cycle
ALE
PSEN
RD / WR
Port 0
Inst Inst Inst Inst
Data
Inst Inst
Port 2
LSB LSB LSB LSB
MOVX
Instruction
Fetch
MSB
Memory Access (Stretch = 4)
LSB
LSB LSB
ALE
MOVX Instruction (Page hit)
1st 2nd
Cycle Cycle
3rd
Cycle
4th
Cycle
5th
Cycle
PSEN
RD / WR
Port 0
Inst Inst Inst Inst
Port 2
LSB LSB LSB LSB
MOVX
Instruction
Fetch
Memory Access (Stretch = 4)
9th
Cycle
Data
Inst Inst Inst
LSB LSB LSB LSB
Figure 10 shows the timing relationship for a slow peripheral interface (stretch value = 4). Note that a
page hit data-memory cycle is shorter than a page miss data-memory cycle. The ALE pulse width is also
stretched by a stretch cycle in the case of page miss.
The stretched data-memory bus-cycle timing relationship for PAGES = 11 is identical to non-page mode
operation since the basic data-memory cycle always contains four system clocks in this page mode
operation.
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