DS89C420 Datasheet, PDF (13/59 Pages) Dallas Semiconductor – Ultra-High-Speed Microcontroller

DS89C420
Memory Organization
There are three distinct memory areas in the DS89C420: scratchpad registers, program memory, and data
memory. All registers are located on-chip but the program and data memory spaces can be either on-chip,
off-chip, or both. There are 16kB of on-chip program memory implemented in flash memory and 1kB of
on-chip data memory space that can be configured as program space using the PRAME bit in the
ROMSIZE feature. The DS89C420 uses a memory-addressing scheme that separates program memory
from data memory. The program and data segments can be overlapped since they are accessed in different
ways. If the maximum address of on-chip program or data memory is exceeded, the DS89C420 performs
an external memory access using the expanded memory bus. The PSEN signal goes active low to serve
as a chip enable or output enable when performing a code fetch from external program memory. MOVX
instructions activate the RD or WR signal for external MOVX data memory access. The lower 128
bytes of on-chip flash memory store reset and interrupt vectors. The program memory ROMSIZE feature
allows software to dynamically configure the maximum address of on-chip program memory. This allows
the DS89C420 to act as a bootloader for an external flash or NV SRAM. It also enables the use of the
overlapping external program spaces.
256 bytes of on-chip RAM serve as a register area and program stack, which are separated from the data
memory.
Register Space
Registers are located in the 256 bytes of on-chip RAM, which can be divided into two subareas of 128
bytes each as illustrated in Figure 2. Separate classes of instructions are used to access the registers and
the program/data memory. The upper 128 bytes are overlapped with the 128 bytes of SFRs in the memory
map. The upper 128 bytes of scratchpad RAM are accessed by indirect addressing, and the SFR area is
accessed by direct addressing. The lower 128 bytes can be accessed by direct or indirect addressing.
There are four banks of eight individual working registers in the lower 128 bytes of scratchpad RAM.
The working registers are general-purpose RAM locations that can be addressed within the selected bank
by any instructions that use R0–R7. The register bank selection is controlled through the program status
register in the SFR area. The contents of the working registers can be used for indirectly addressing the
upper 128 bytes of scratchpad RAM.
To support the Boolean operations, there are individually addressable bits in both the RAM and SFR
areas. In the scratchpad RAM area, registers 20h–2Fh are bit-addressable by software using Boolean
operation instructions.
Another use of the scratchpad RAM area is for the stack. The stack pointer in the SFRs is used to select
storage locations for program variables and for return addresses of control operations.
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