DS89C420 Datasheet, PDF (26/59 Pages) Dallas Semiconductor – Ultra-High-Speed Microcontroller

DS89C420
The first page mode (page mode 1) external bus structure uses P2 as the primary address bus,
(multiplexing both the most significant byte (MSB) and least significant byte (LSB) of the address for
each external memory cycle) and P0 is used as the primary data bus. During external code fetches, P0 is
held in a high-impedance state by the processor. Op codes are driven by the external memory onto P0 and
latched at the end of the external fetch cycle at the rising edge of PSEN . During external data read/write
operations, P0 functions as the data I/O bus. It is held in a high-impedance state for external reads from
data memory, and driven with data during external writes to data memory.
§ A page miss occurs when the MSB of the subsequent address is different from the last address.
The external memory machine cycle can be 2, 4, or 8 system clocks in length for a page miss.
§ A page hit occurs when the MSB of the subsequent address does not change from the last address.
The external memory machine cycle can be 1, 2, or 4 system clocks in length for a page hit.
During a page hit, P2 drives Addr0–7 of the 16-bit address while the most significant address byte is held
in the external address latches. PSEN , RD , and WR strobe accordingly for the appropriate operation on
the P0 data bus. There is no ALE assertion for page hits.
During a page miss, P2 drives the Addr [8:15] of the 16-bit address and holds it for the duration of the
first half of the memory cycle to allow the external address latches to latch the new most significant
address byte. ALE is asserted to strobe the external address latches. During this operation, PSEN , RD ,
and WR are all held in inactive states and P0 is in a high-impedance state. The second half of the
memory cycle is executed as a page-hit cycle and the appropriate operation takes place.
A page miss can occur at set intervals or during external operations that require a memory access into a
page of memory that has not been accessed during the last external cycle. Generally, the first external
memory access causes a page miss. The new page address is stored internally, and is used to detect a page
miss for the current external memory cycle.
Note that there are a few exceptions for this mode of operation when PAGES1 and PAGES2 are set to
00b:
§ PSEN is asserted for both page hit and page miss for a full clock cycle.
§ The execution of external MOVX instruction causes a page miss.
§ A page miss occurs when fetching the next external instruction following the execution of an external
MOVX instruction.
Figure 7 shows the external memory cycle for this bus structure. The first case illustrates a back-to-back
execution sequence for 1-cycle page mode (PAGES1 = PAGES0 = 0b). PSEN remains active during
page hit cycles, and page misses are forced during and after MOVX executions, independent of the most
significant byte of the subsequent addresses. The second case illustrates a MOVX execution sequence for
2-cycle page mode (PAGES1 = 0 and PAGES0 = 1). PSEN is active for a full clock cycle in code
fetches. Note that the page misses in this sequence are caused by changing the MSB of the data address.
The third case illustrates a MOVX execution sequence for 4-cycle page mode (PAGES1 = 1 and
PAGES0 = 0). There is no page miss in this execution cycle because the most significant byte of the data
address is assumed to match the last program address.
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