DS89C420 Datasheet, PDF (27/59 Pages) Dallas Semiconductor – Ultra-High-Speed Microcontroller

DS89C420
The second page mode (page mode 2) external bus structure multiplexes the most significant address byte
with data on P2, and uses P0 for the least significant address byte. This bus structure is used to speed up
external code fetches only. External data-memory access cycles are identical to the non-page mode except
for the different signals on P0 and P2. Figure 8 illustrates the memory cycle for external code fetches.
Figure 7. Page Mode 1, External Memory Cycle (CD1:CD0 = 10)
Internal Memory Cycles
XTAL1
ALE
PSEN
RD / WR
Port 0
External Memory Cycles
Inst Inst ^{MOVX MOVX}
Data
Inst
Data
Port 2
ALE
MSB LSB
Page Miss
LSB LSB LSB MSB LSB
Page Hit
Data Access
MOVX executed
MSB LSB MSB LSB MSB
Page Miss
Data Access
MOVX executed
PSEN
RD / WR
Port 0
Port 2
ALE
PSEN
RD / WR
Port 0
Port 2
MOVX
Inst
Data
MSBAdd
LSB Add
Page Miss
LSB Add
MSBAdd
LSB Add
Page Hit
Data Access
MOVX executed
MSBAdd
Page Miss
next instruction
MSBAdd
Page Miss
Inst
LSB Add
Data
LSB Add
Data Access
PAGES=00
PAGES=01
PAGES=10
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