DS89C420 Datasheet, PDF (33/59 Pages) Dallas Semiconductor – Ultra-High-Speed Microcontroller

DS89C420
Interrupts
The DS89C420 provides 13 interrupt vector sources. All interrupts, with the exception of the power-fail,
are controlled by a series combination of individual enable bits and a global enable (EA) in the interrupt
enable register (IE.7). Setting EA to a logic 1 allows individual interrupts to be enabled. Setting EA to a
logic 0 disables all interrupts regardless of the individual interrupt enable settings. The power-fail
interrupt is controlled by its individual enable only.
The interrupt enables and priorities are functionally identical to those of the 80C52, except that the
DS89C420 supports five levels of interrupt priorities instead of the original two.
Interrupt Priority
There are five levels of interrupt priority: level 4 to 0. The highest interrupt priority is level 4, which is
reserved for the power-fail interrupt. All other interrupts have individual priority bits in the interrupt
priority registers to allow each interrupt to be assigned a priority level from 3 to 0. The power-fail
interrupt always has the highest priority if it is enabled. All interrupts also have a natural hierarchy. In
this manner, when a set of interrupts has been assigned the same priority, a second hierarchy determines
which interrupt is allowed to take precedence. The natural hierarchy is determined by analyzing potential
interrupts in a sequential manner with the order listed in Table 12.
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