DS89C420 Datasheet, PDF (28/59 Pages) Dallas Semiconductor – Ultra-High-Speed Microcontroller

DS89C420
Figure 8. Page Mode 2, External Code Fetch Cycle (CD1:CD0 = 10)
Internal Memory Cycles
XTAL1
Ext Code Fetches
Page Miss
C1 C2 C3 C4
Page Hit
Page Hit
C1 C2 C1 C2
ALE
PSEN
Port 0
LSB Add
LSB Add
LSB Add
Port 2
MSB Add
Data
Data
Data
Stretch External Data Memory Cycle in Page Mode
The DS89C420 allows software to adjust the speed of external data memory access by stretching the
memory bus cycle in page mode operation just like non-page mode operation. The following tables
summarize the stretch values and their effects on the external MOVX-memory bus cycle and the control
signals’ pulse width in terms of the number of oscillator clocks. A stretch machine cycle always contains
four system clocks, independent of the logic value of the page mode select bits.
Table 8. Page Mode 1, Data Memory Cycle Stretch Values
(Pages1:Pages0 = 00)
MD2:MD0
STRETCH
CYCLES
000
0
001
1
010
2
011
3
100
7
101
8
110
9
111
10
RD _/ WR _{PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)}
4X/2X, CD1,
CD0 = 100
4X/2X, CD1,
CD0 = 000
4X/2X, CD1,
CD0 = X10
4X/2X, CD1,
CD0 = X11
0.25
0.5
1
1024
0.75
1.5
3
3072
1.75
3.5
7
7168
2.75
5.5
11
11,264
3.75
7.5
15
15,360
4.75
9.5
19
19,456
5.75
11.5
23
23,552
6.75
13.5
27
27,648
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