CY8C22213 Datasheet, PDF (36/304 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

3. CPU Core (M8C)
CY8C22xxx Preliminary Data Sheet
exception of jmp instructions) incur an extra M8C clock
cycle as the upper byte of the PC is incremented.
The register address space is used to configure the PSoC
microcontroller’s programmable blocks. It consists of two
banks of 256 bytes each. To switch between banks, the XIO
bit in the Flag register is set or cleared (set for Bank1,
cleared for Bank0). The common convention is to leave the
bank set to Bank0 (XIO cleared), switch to Bank1 as
needed (set XIO), then switch back to Bank0.
A
X
PC
SP
F
IOW IOR XIO
DB[7:0]
DA[7:0]
M8C
MW MR
Registers
Bank 0
256 Bytes
RAM
Page 0
256 Bytes
ID[7:0]
ROM
SROM
PC[15:0]
Bank 1
256 Bytes
LEGEND
M: Total number of Flash blocks in device
XIO: Register bank selection
IOR: Register read
IOW: Register write
MR: Memory read
MW: Memory write
Flash
M x 64
Byte Blocks
Figure 3-1. M8C Microcontroller Address Spaces
36
Document No. 38-12009 Rev. *D
December 22, 2003