CY8C22213 Datasheet, PDF (211/304 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

CY8C22xxx Preliminary Data Sheet
17. Digital Blocks
SS Forced Low
SS
SCLK (Mode 0)
SCLK (Mode 1)
Transfer in Progress
SS Toggled on a Message Basis
Transfer in Progress
SS
SCLK (Mode 0)
SCLK (Mode 1)
Transfer in Progress
SS Toggled on Each Byte
Transfer in Progress
SS
SCLK (Mode 0)
SCLK (Mode 1)
Transfer in Progress
Figure 17-17. SPI Status Timing for Modes 0 and 1
MODE 2,3 (Phase=1) Output on leading edge. Input on trailing edge.
User writes
the next byte.
SCLK,Polarity=0 (Mode 2)
SCLK, Polarity=1 (Mode 3)
MOSI
7
6
5
4
3
2
10
7
MISO
7
6
5
4
3
2
10
7
SS_
TX REG EMPTY
RX REG FULL
SPI COMPLETE
OVERRUN
TX Buffer is
transferred into
the shifter
Last bit of byte
is received.
All clocks and data for
this byte completed.
Overrun occurs ½
cycle before the
last bit is received.
TX Buffer is
transferred into
the shifter.
Figure 17-18. SPI Status Timing for Modes 2 and 3
December 22, 2003
Document No. 38-12009 Rev. *D
211