CY8C22213 Datasheet, PDF (104/304 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

13. Register Details
13.1.19
ASY_CR
Analog Synchronization Control Register
CY8C22xxx Preliminary Data Sheet
Individual Register Names and Addresses
ASY_CR: 0,65h
7
Access : POR
Bit Name
6
5
4
W:0
SARCNT[2:0]
3
2
1
RW : 0
RW : 0
SARSIGN
SARCOL[1]
0
RW : 0
SYNCEN
For additional information, reference the “Register Definitions” on page 228 in the Analog Interface chapter.
Bit
[7]
[6:4]
Name
Reserved
SARCNT[2:0]
[3]
SARSIGN
[2]
SARCOL[1]
[1]
Reserved
[0]
SYNCEN
Description
Initial SAR count. This field is initialized to the number of SAR bits to process.
Note Any write to the SARCNT bits, other than 0, will result in a modification of the read back of any
analog register in the analog array. These bits must always be zero, except for SAR processing.
This bit adjusts the SAR comparator based on the type of block addressed. In a DAC configuration
with more than one analog block (more than 6-bits), this bit should be set to ‘0’ when processing the
most significant block, and ‘1’ when processing the least significant block. This is because the least
significant block is an inverting input to the most significant block.
The selected column corresponds with the position of the SAR comparator block. Note that the com-
parator and DAC can be in the same block.
00b Analog Column 0 is the source for SAR comparator
01b Analog Column 1 is the source for SAR comparator
Set to ‘1’, will stall the CPU until the rising edge of PHI1, if a write to a register within an analog Switch
Cap block takes place.
0
CPU stalling disabled.
1
CPU stalling enabled.
104
Document No. 38-12009 Rev. *D
December 22, 2003