CY8C22213 Datasheet, PDF (15/304 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

CY8C22xxx Preliminary Data Sheet
Top-Level Architecture
The figure below illustrates the top-level architecture of the PSoC CY8C22xxx.
SYSTEM BUS
SECTION A OVERVIEW
Port 1
Port 0
Analog
Drivers
Global Digital Interconnect
Global Analog Interconnect
SRAM
PSoC CORE
Supervisory ROM (SROM) Flash Nonvolatile Memory
Interrupt
Controller
CPU Core (M8C)
Sleep and
Watchdog
24 MHz Internal Main
Oscillator (IMO)
Internal Low Speed
Oscillator (ILO)
Phased Locked Loop (PLL)
32 kHz Crystal
Oscillator (ECO)
DIGITAL SYSTEM
Digital PSoC
Block Array
DB DB DC DC
Digital Row
ANALOG SYSTEM
Analog PSoC
Block Array
CT
Analog
Refs
Analog
Input
Muxing
SC
SC
Analog Column
Digital
Clocks
Decimator
I²C
POR and LVD
System Resets
SYSTEM RESOURCES
PSoC CY8C22xxx Top-Level Block Diagram
Internal
Voltage
Reference
December 22, 2003
Document No. 38-12009 Rev. *D
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