CY8C22213 Datasheet, PDF (181/304 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

15. Array Digital Interconnect (ADI)
This chapter presents the Array Digital Interconnect (ADI). The digital PSoC array uses a scalable architecture that is
designed to support from one to four digital PSoC rows, as defined in the Row Digital Interconnect (RDI) chapter on page
183. The digital PSoC array does not have any configurable interconnect; therefore, there are no associated registers.
15.1 Architectural Description
The Array Digital Interconnect (ADI) is shown in Figure 15-1.
The ADI is not configurable; therefore, the information in this
chapter is provided to improve the reader’s understanding of
the structure.
DB[7:0] GIE[7:0]
DBI
GIO[7:0]
VC2
VC3
CLK32K
VC1
SYSCLKX2
ACMP[3:0]
GOE[7:0]
GOO[7:0]
INT[23:8]
BCrow0
Hi
Hi
Hi
Low
Low
Low
BCrow0
BCrow1
BCrow2
BCrow3
Previous block data
Previous block clk
GIO[7:0]
GlE[7:0]
Digital PSoC Block Row 0
FPB
TPB
DB[7:0]
DBB00 DBB01 DCB02 DCB03
DBI
BCw
GOO[7:0]
GOE[7:0]
INT[3:0]
TNB
FNB
BCrow0
Low
Figure 15-1. Digital PSoC Block Array Structure
The different members of the PSoC family have varying
numbers of digital PSoC blocks in the digital array. These
blocks are arranged into rows and the ADI provides a regu-
lar interconnect architecture between the Global Digital
Interconnect (GDI) and the Row Digital Interconnect (RDI),
regardless of the number of rows available in a particular
device. The most important aspect of the ADI and the digital
PSoC rows is that all digital PSoC rows have the same con-
nections to global inputs and outputs. The connections that
make a row’s position unique are explained in the following
bulleted list.
s Register Address: Clearly rows and the blocks within
them need to have unique register addresses.
s Interrupt Priority: Each digital PSoC block has its own
interrupt priority and vector. A row’s position in the array
determines the relative priority of the digital PSoC blocks
within the row. The lower the row number the higher the
interrupt priority and the lower the interrupt vector
address.
s Broadcast: Each digital PSoC row has an internal broad-
cast net that may be either driven internally, by one of
the four digital PSoC blocks, or driven externally. In the
case where the broadcast net is driven externally, the
source may be any one of the other rows in the array.
Therefore, depending on the row’s position in the array,
it will have different options for driving its broadcast net.
s Chaining Position: Rows in the array form a string of dig-
ital blocks equal in length to the number of rows multi-
plied by four. The first block in the first row and the last
block in the last row are not connected; therefore, the
array does not form a circle. The first row in the array will
have its previous chaining inputs tied low. If there is a
second row in the array, the next chaining outputs will be
connected to the next row. For the last row in the array,
the next inputs are tied low.
December 22, 2003
Document No. 38-12009 Rev. *D
181