CY8C22213 Datasheet, PDF (260/304 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

25. Decimator
CY8C22xxx Preliminary Data Sheet
25.2.2 DEC_DL Register
The Decimator Data Low register (DEC_DL) is a dual pur-
pose register. When the register is read the least significant
byte of the 16-bit decimator value is returned. Depending on
how the decimator is configured, this value is either the
result of the second integration or the lower byte of the 16-
bit counter. The second function of the DEC_DL register is
activated when ever the register is written: That function is
to clear the decimator value. When the DEC_DL register is
written the decimator's value will be cleared regardless of
the value written. Either the DEC_DL or DEC_DH register
may be written to clear the decimator's value. Note that this
register does not reset to 00h. The DEC_DL register resets
to an indeterminate value.
For additional information, reference the DEC_DL register
on page 139.
25.2.3 DEC_CR0 Register
This register contains control bits to access hardware sup-
port for both the Incremental ADC and the DELISG ADC.
For Incremental support, the upper four bits, IGEN[3:0],
select which column comparator bit will be gated by the out-
put of a digital block. The output of that digital block is typi-
cally a PWM signal; the high time of which corresponds to
the ADC conversion period. This ensures that the compara-
tor output is only processed for the precise conversion time.
The digital block selected for the gating function is controlled
by ICLKS0 in this register and ICLKS1 in DEC_CR1. Up to
one of 16 digital blocks may be selected, depending on your
specific chip resources.
The DELSIG ADC uses the hardware decimator to do a por-
tion of the post processing computation on the comparator
signal. DCOL[1:0] selects the column source for the decima-
tor data (comparator bit) and clock input (PHI clocks).
In addition, the decimator requires a timer signal to sample
the current decimator value to an output register that may
subsequently be read by the CPU. This timer period is set to
be a function of the DELSIG conversion time and may be
selected from up to one of 16 digital blocks (depending on
your specific chip resources) with bit DCLKS0 and DCLKS1
in DEC_CR1.
For additional information, reference the DEC_CR0 register
on page 140.
25.2.4 DEC_CR1 Register
Bit 7: ECNT. The ECNT bit is a mode bit that controls the
operation of the decimator hardware block. By default, the
decimator is set to a double integrate function, for use in
hardware DELSIG processing. When the ECNT bit is set,
the decimator block converts to a single integrate function.
This gives the equivalent of a 16-bit counter suitable for use
in hardware support for an Incremental ADC function.
Bit 6: IDEC. Any function using the decimator requires a
digital block timer to sample the current decimator value.
Normally, the positive edge of this signal will cause the deci-
mator output to be sampled. However, when the IDEC bit is
set, the negative edge of the selected digital block input will
cause the decimator value to be sampled.
Bits 5 and 4: Reserved.
Bit 3: ICLKS1. The ICLKS1 bit in this register selects the
digital block sources for Incremental and DELSIGN ADC
hardware support (see the DEC_CR0 register).
Bits 2 and 1: Reserved.
Bit 0: DCLKS1. The DCLKS1 bit in this register selects the
digital block sources for Incremental and DELSIGN ADC
hardware support (see the DEC_CR0 register).
For additional information, reference the DEC_CR1 register
on page 141.
260
Document No. 38-12009 Rev. *D
December 22, 2003