CY8C22213 Datasheet, PDF (265/304 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

CY8C22xxx Preliminary Data Sheet
26. I2C
26.3 Register Definitions
The I2C block contains four registers, all of which reside in
User IO space: Configuration Register (I2C_CFG), Status
and Control Register (I2C_SCR), Master Status and Control
Register (I2C_MSCR), and Data Register (I2C_DR).
The Configuration register is used to set the basic operating
modes, baud rate, and selection of interrupts. The Status
and Control register is used by both Master and Slave to
control the flow of data bytes and to keep track of the bus
state during a transfer. Data and address bytes are written
to and read from the Data Register. The Master Status and
Control register implements I2C framing controls and pro-
vides Bus Busy status.
26.3.1 I2C_CFG Register
This register is the I2C configuration register and contains
the configuration bits for both Master and Slave mode oper-
ation. These bits control baud rate selection and optional
interrupts. These values are typically set once for a given
configuration. The bits in this register are all R/W.
Table 26-2. I2C_CFG Configuration Register
Bit Access Description
Mode
0
R/W
Enable Slave
‘0’ = Disabled
Master/
Slave
‘1’ = Enabled
1
R/W
Enable Master
‘0’ = Disabled
Master/
Slave
‘1’ = Enabled
3:2 R/W
Clock Rate
00 = 100K, Standard Mode
Master/
Slave
01 = 400K Fast Mode
10 = 50K Standard Mode
11 = Reserved
4
R/W
Stop IE
Stop interrupt enable.
Master
Only
0 = Disabled.
1 = Enabled. An interrupt is generated on
the detection of a Stop Condition.
5
R/W
Bus Error IE
Stop interrupt enable.
Master/
Slave
0 = Disabled.
1 = Enabled. An interrupt is generated on
the detection of a Bus Error.
6
R/W
I2C Pin Select
0 = P1[7], P1[5]
Master/
Slave
1 = P1[1], P1[0]
Bit 7: Reserved.
Bit 6: PSelect. With the default value of zero, the I2C pins
are P1[7] for clock and P1[5] for data. When this bit is set,
the pins for I2C switch to P1[1] for clock and P1[0] for data.
This bit may not be changed while either the Enable Master
or Enable Slave bits are set. However, the PSelect bit may
be set at the same time as the enable bits. The two sets of
pins I2C may be used on are not equivalent. The default set,
P1[7] and P1[5], are the preferred set. The alternate set,
P1[1] and P1[0], are provided so that I2C may be used with
8-pin PSoC parts.
If In-circuit System Serial Programming (ISSP) is to be used
and the alternate I2C pin set is also used, it is necessary to
take into account the interaction between the PSoC Test
Controller and the I2C bus. The interface requirements for
ISSP should be reviewed to ensure that they are not vio-
lated.
Even if ISSP is not going to be used, pins P1[1] and P1[0]
will respond differently to a POR or XRES event than other
IO pins. After an XRES, event both pins will be pulled down
to the ground by going into the resistive zero drive mode
before reaching the High-Z drive mode. After a POR event,
P1[0] will drive out a one, then go to the resistive zero state
for some time, and finally reach the High-Z drive mode state.
After POR, P1[1] will go into a resistive zero state for a while
before going to the High-Z drive mode.
Another issue with selecting the alternate I2C pins set is that
these pins are also the crystal pins. Therefore, a crystal may
not be used when the alternate I2C pin set is selected.
Bit 5: Bus Error IE (Interrupt Enable). This bit controls
whether the detection of a Bus Error will generate an inter-
rupt. A Bus Error is typically a misplaced Start or Stop. See
the Bus Error status bit description for a definition.
This is an important interrupt with regards to Master opera-
tion. When there is a misplaced Start or Stop on the I2C bus
all Slave devices (including this device, if Slave mode is
enabled) will reset the bus interface and synchronize to this
signal. However, when the hardware detects a Bus Error in
Master mode operation, the device will release the bus and
transition to an idle state. In this case, a Master operation in
progress will never have any further status or interrupts
associated with it and therefore the Master may not be able
to determine the status of that transaction. An immediate
bus error interrupt will inform the Master that this transfer did
not succeed.
Bit 4: Stop IE (Interrupt Enable). When this bit is set, a
Master or Slave can interrupt on Stop detection. The status
bit associated with this interrupt is the Stop Status bit in the
Slave Status and Control register. When the Stop Status bit
transitions from ‘0’ to ‘1’, the interrupt is generated. It is
important to note that the Stop Status bit is not automatically
cleared. Therefore, if it is already set, no new interrupts will
be generated until it is cleared by firmware and a subse-
quent Stop condition is generated.
Bits 3 and 2: Clock Rate. The Clock Rate bits offer a
selection of four sampling and bit rates. All block clocking is
based on the SYSCLK input, which is nominally 24 MHz.
The sampling rate and the baud rate are determined as fol-
lows:
s Sample Rate = SYSCLK/Pre-scale Factor
s Baud Rate = 1/(Sample Rate X Samples per Bit)
December 22, 2003
Document No. 38-12009 Rev. *D
265