CY8C22213 Datasheet, PDF (237/304 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

21. Analog Reference
This chapter discusses the Analog Reference generator and its associated register. This device uses a fixed analog ground of
Vdd/2.
Table 21-1. Analog Reference Register
Address
Name
0,63h
ARF_CR
Bit 7
Bit 6
HBE
Bit 5
Bit 4
REF[2:0]
Bit 3
Bit 2
Bit 1
PWR[2:0]
Bit 0
Access
RW : 00
21.1 Architectural Description
Vdd
The PSoC device is a single supply part, with no negative
voltage available or applicable. Analog ground (AGND) is
constructed near mid-supply. This ground is routed to all
analog blocks and separately buffered within each block.
Note that there may be a small offset voltage between buff-
ered analog grounds. RefHi and RefLo signals are gener-
ated, buffered, and routed to the analog blocks. RefHi and
RefLo are used to set the conversion range (i.e., span) of
analog to digital (ADC) and digital to analog (DAC) convert-
ers.
The reference array supplies voltage to all blocks and cur-
rent to the Switched Capacitor blocks. At higher block clock
rates, there is increased reference current demand; the ref-
erence power should be set equal to the highest power level
of the analog blocks used.
RefHi
Vss
RefHi to Analog Blocks
x1
AGND
(Vdd/2)
RefLo to Analog Blocks
AGND
V _{re fh i}
Figure 21-2. Analog Reference Control Schematic
VAGND
V _{re flo w}
Vss
Figure 21-1. Reference Structure
RefLo
December 22, 2003
Document No. 38-12009 Rev. *D
237