CY8C22213 Datasheet, PDF (271/304 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

CY8C22xxx Preliminary Data Sheet
26. I2C
26.4.2 Enable and Command Synchronization
Figure 26-5 illustrates an all block reset (except for the
I2C_CFG register) is asserted when the block is disabled.
When either the Enable Master or Enable Slave bit is set,
the block reset is negated on the next positive edge of
SYSCLK, which ensures a full SYSCLK cycle of setup time
on the next clock edge.
Figure 26-6 illustrates a Start Gen command or I2C_SCR
write after Byte Complete is resynchronized to the following
block clock edge. I2C processing continues on the selected
block clock following this resync clock edge.
IOW
IOW
SYSCLK
BLOCK
CLOCK
CMD_GO
I2C_RESET
PRESCALER
STATE
IDLE or WAIT
Figure 26-6. I2C Command
NEXT STATE
CLOCK
Figure 26-5. I2C Enable
26.4.3 Basic Input/Output Timing
Figure 26-7 illustrates basic input output timing that is valid
for both 16x sampling and 32x sampling. For 16x sampling,
N=4 and for 32x sampling N=12. N is derived from the half
bit rate sampling of eight and 16 clocks, respectively, minus
the input latency of three (count of 4 and 12 correspond to 5
and 13 clocks).
CLOCK
SCL
SCL_IN
CLK CTR
N
SHIFT
SDA_IN
SDA_OUT
LOST ARB
STATUS
...
...
...
...
...
...
0
1 2 ^... N
0
1 2 ... N
0
...
...
...
...
...
...
Figure 26-7. Basic Input/Output Timing
December 22, 2003
Document No. 38-12009 Rev. *D
271