CY8C22213 Datasheet, PDF (207/304 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

CY8C22xxx Preliminary Data Sheet
17. Digital Blocks
17.3.3.1 Changing the PWM Duty Cycle
Under normal circumstances, the Dead Band period is less
than the minimum PWM high or low time. As an example,
consider the following diagram where the low of the PWM is
4 clocks and the dead band period is 2 clocks and the high
time of the PHI2 is 2 clocks.
CLK
PWM
PHI1
PHI2
4
2
2
2
Figure 17-9. DB High Time is PWM Width Minus DB
Period
In Figure 17-10, you reduce the width of the PWM low time
by 1 clock (to 3 clocks). The dead band period remains the
same, but the high time for PHI2 is reduced by 1 clock (to 1
clock). Of course the opposite phase, PHI1, increases in
length by 1 clock.
CLK
WM
PHI1
PHI2
3
1
2
2
Figure 17-10. DB High Time is Reduced as PWM Width
is Reduced
If the width of the PWM low time is reduced to a point where
it is equal to the dead band period, the corresponding
phase, PHI2, disappears altogether. Note that after the ris-
ing edge of the PWM the opposite phase still has the pro-
grammed dead band. Figure 17-11 shows an example
where the Dead Band period is 2 and the PWM width is 2. In
this case, the high time of PHI2 is 0 clocks. Note that the
Phase 1 dead band time is still 2 clocks.
CLK
PWM
PHI1
PHI2
2
2
2
Figure 17-11. PWM Width Equal to Dead Band Period
In the case where the dead band period is greater than the
high or low of the PWM reference, the output of the associ-
ated phase will not be asserted high.
17.3.3.2 Kill Operation
It is assumed that the KILL input will not be synchronized at
the row input. (This is not a requirement; however, if syn-
chronized the KILL operation will have up to two 24 MHz
clock cycles latency, which is undesirable.) To support the
restart modes, the negation of KILL is internally (in the
block) synchronized to the 24 MHz system clock.
There are three KILL modes supported. In all cases, the
KILL signal asynchronously forces the outputs to logic '0'.
The differences in the modes come from how dead band
processing is restarted.
1. Synchronous Restart Mode: When KILL is asserted
high internal state is held in reset and the initial dead
band period is reloaded into the counter. While KILL is
held high, incoming PWM reference edges are ignored.
When KILL is negated, the next incoming PWM refer-
ence edge restarts dead band processing. See
Figure 17-12.
2. Asynchronous Restart Mode: When KILL is asserted
high, internal state is not affected. When KILL is
negated, outputs are restored, subject to a minimum dis-
able time between one-half and one and one-half clock
cycle. See Figure 17-13.
3. Disable Mode: There is no specific timing associated
with Disable Mode. The block is disabled and the user
must re-enable the function in firmware to continue pro-
cessing.
PWM
REFERENCE
PHI1
PHI2
KILL
Short KILL, outputs off for
remainder of current cycle.
Operation resumes on
the next PWM edge.
PWM
REFERENCE
PHI1
PHI2
KILL
Output is off for duration These edges Operation resumes
of KILL on time.
are skipped. on this edge.
Figure 17-12. Synchronous Restart KILL Mode
December 22, 2003
Document No. 38-12009 Rev. *D
207