CY8C22213 Datasheet, PDF (31/304 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

SECTION B CORE ARCHITECTURE
The Architecture section discusses the core components of the PSoC device and the registers associated with those compo-
nents. This section encompasses the following chapters:
s CPU Core (M8C) on page 35
s Internal Main Oscillator (IMO) on page 63
s Supervisory ROM (SROM) on page 45
s Internal Low Speed Oscillator (ILO) on page 65
s Interrupt Controller on page 51
s 32 kHz Crystal Oscillator (ECO) on page 67
s General Purpose IO (GPIO) on page 55
s Phase Locked Loop (PLL) on page 71
s Analog Output Drivers on page 61
s Sleep and Watchdog on page 73
Top-Level Core Architecture
The figure below displays the top-level architecture of the PSoC’s core. Each component of the figure is discussed at length
in this section.
Port 1
Port 0
Analog
Drivers
SYSTEM BUS
SRAM
Interrupt
Controller
Supervisory ROM (SROM) Flash Nonvolatile Memory
CPU Core (M8C)
Sleep and
Watchdog
24 MHz Internal Main
Oscillator (IMO)
Internal Low Speed
Oscillator (ILO)
Phased Locked Loop (PLL)
32 kHz Crystal
Oscillator (ECO)
PSoC Core Block Diagram
December 22, 2003
Document No. 38-12009 Rev. *D
31