CY8C22213 Datasheet, PDF (247/304 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

CY8C22xxx Preliminary Data Sheet
23. Continuous Time Block
23.2 Register Definitions
23.2.1 ACBxxCR0 Register
Bits 7 to 4: RTapMux[3:0]. These bits, in combination with
the EXGAIN bit, B0, of the CR3 register, control the center
tap of the resistor string.
Bit 3: Gain. This bit controls whether the resistor string is
connected around the opamp as for gain (center tap to
inverting opamp input) or for loss (center tap to output of the
block). Note that setting Gain alone does not guarantee a
gain or loss block. Routing of the other ends of the resistor
determine this.
Bit 2: RTopMux. This bit controls the top end of the resistor
string, which can either be connected to Vdd or to the
opamp output.
Bits 1 and 0: RBotBux[1:0]. These bits, in combination
with the INSAMP bit, B1, of the CR3 register, control the
connection of the bottom end of the resistor string.
For additional information, reference the ACBxxCR0 register
on page 107.
23.2.2 ACBxxCR1 Register
Bit 7: AnalogBus. This bit controls the analog output bus.
A CMOS switch connects the opamp output to the analog
bus.
Bit 6: CompBus. This bit controls a tri-state buffer that
drives the comparator logic. If no block in the analog column
is driving the comparator bus, it will be driven low externally
to the blocks.
Bits 5, 4, and 3: NMux[2:0]. These bits control the multi-
plexing of inputs to the inverting input of the opamp. There
are seven input choices from outside the block, plus an
internal feedback selection.
Bits 2, 1, and 0: PMux[2:0]. These bits control the multi-
plexing of inputs to the non-inverting input of the opamp.
There are seven input choices from outside the block, plus
an internal feedback selection.
For additional information, reference the ACBxxCR1 register
on page 108.
23.2.3 ACBxxCR2 Register
Bit 7: CPhase. This bit controls which internal clock phase
the comparator data is latched on.
Bit 6: CLatch. This bit controls whether the latch is active
or if it is always transparent.
Bit 5: CompCap. This bit controls whether the compensa-
tion capacitor is switched in or not in the opamp. By not
switching in the compensation capacitance, a much faster
response can be obtained, if the amplifier is being used as a
comparator.
Bit 4: TMUXEN. If the TMUXEN bit is high, then the value
of TestMux[1:0] determines which testmux input is con-
nected to the ABus for that particular continuous time block.
If the TMUXEN bit is low, then none of the testmux inputs
are connected to the ABus regardless of the value of Test-
Mux[1:0].
Bits 3 and 2: TextMux[1:0]. TestMux selects block bypass
mode.
Bits 1 and 0: PWR[1:0]. Power is encoded to select 1 of 3
power levels or power down (Off). The blocks power up in
the off state. Combined with the Turbo mode, this provides 6
power levels. Turbo mode is controlled by the HBE bit of the
Analog Reference Control Register.
For additional information, reference the ACBxxCR2 register
on page 109.
23.2.4 ACBxxCR3 Register
Bits 7 to 4: Reserved.
Bit 3: LPCMPEN. Each continuous time block has a low
power comparator connected in parallel with the block’s
main opamp/comparator. The low power comparator is used
in situations where low power is more important than low
noise, low offset, and high speed. The low power compara-
tor operates when the LPCMPEN bit is set high. Since the
main opamp/comparator’s output is connected to the low
power comparator’s output, only one of the comparators
should be active at a particular time. The main opamp/com-
parator is powered down by setting ACBxxCR2: PWR[1:0]
to 00b, or setting ARF_CR: PWR[2:0] to x00b. The low
power comparator is unaffected by the PWR bits in
ACBxxCR2 and ARF_CR.
December 22, 2003
Document No. 38-12009 Rev. *D
247