CY8C22213 Datasheet, PDF (233/304 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

CY8C22xxx Preliminary Data Sheet
ACB
01
ASD
011
ASC
21
Figure 19-6. CMux Connections
ACB
01
NC
ASD
11
1
NC
ASC
21
(2)
NC
19. Analog Array
In the Continuous Time (CT) analog blocks, the CPhase and
CLatch bits inside the Analog Continuous Time Type B
Block xx Control Register 2 determine whether the output
signal on the comparator bus is latched inside the block, and
if it is, which clock phase it is latched on.
In the SC analog blocks, the output on the comparator bus is
always latched. The ClockPhase bit in the Analog Switch-
Cap Type B Block xx Control Register 0 or the Analog
SwitchCap Type B Block xx Control Register 0 determines
the phase on which this data is latched and available.
19.2 Temperature Sensing
Capability
A temperature-sensitive voltage, derived from the bandgap
sensing on the die, is buffered and available as an analog
input into the Analog Switch Cap Type C Block ASC21.
Temperature sensing allows protection of device operating
ranges for fail-safe applications. Temperature sensing, com-
bined with a long sleep timer interval (to allow the die to
approximate ambient temperature), can give an approxi-
mate ambient temperature for data acquisition and battery
charging applications. The user may also calibrate the inter-
nal temperature rise based on a known current consump-
tion.
The temperature sensor input to the ASC21 block is labeled
VTemp and its associated ground reference is labeled TRef-
GND.
TRefGND
Figure 19-7. BMuxSC/SD Connections
19.1.1 Analog Comparator Bus
Each analog column has a dedicated comparator bus asso-
ciated with it. Every analog PSoC block has a comparator
output that can drive out on this bus. However, the compara-
tor output from only one analog block in a column can be
actively driving the comparator bus for that column at any
one time. The output on the comparator bus can drive into
the digital blocks and is also available to be read in the
CMP_CR register.
The comparator bus is latched before it is available to either
drive the digital blocks or be read in the Analog Comparator
Control Register. The latch for each comparator bus is trans-
parent (the output tracks the input), during the high period of
PHI2. During the low period of PHI2, the latch retains the
value on the comparator bus during the high to low transition
of PHI2.
The output from the analog block that is actively driving the
bus may also be latched internally to the analog block itself.
December 22, 2003
Document No. 38-12009 Rev. *D
233