CY8C22213 Datasheet, PDF (191/304 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

CY8C22xxx Preliminary Data Sheet
17. Digital Blocks
17.1.3 Output De-Multiplexers
Most functions have two outputs: a primary and an auxiliary
output. Each of these outputs may be driven onto the row
output bus. Each de-multiplexer is implemented with four tri-
state drivers. There are two bits to select one of the four and
an additional bit to enable the selected driver.
Clock
Select
16-1
MUX
CLK
ReSync
CLK
Data
Select
16-1
MUX
DATA
Digital
PSoC
Block
Aux
Data
Select
4-1
MUX
Internal Signals for
Carry, Compare,
Enable, Capture,
and Gate chaining
from previous block.
AUX_DATA
CI
CMPI
ENI
CGI
CONFIGURATION
REGISTERS
FUNCTION[7:0]
INPUT[7:0]
OUTPUT[7:0]
Primary Function Output,
clock chaining to next
block.
F1
1-4
DMUX
RO[3:0]
F2
1-4
DMUX
RO[3:0]
INT
Block Interrupt
BC
Broadcast Output
DO
CO
CMPO
ENO
Internal Signals for
Data, Carry,
Compare, Enable,
Capture, and Gate
chaining to next
block.
Figure 17-2. Digital Blocks Top-Level Block Diagram
17.1.4 Block Chaining Signals
Each digital block has the capability to be chained and to
create functions with bit widths greater than eight. There are
signals to propagate information, such as Compare, Carry,
Enable, Capture and Gate, from one block to the next to
implement higher precision functions. The selection made in
the Function register determines which signals are appropri-
ate for the desired function. User Modules that have been
designed to implement digital functions, with greater than 8-
bit width, will automatically make the proper selections of the
chaining signals, to ensure the correct information flow
between blocks.
December 22, 2003
Document No. 38-12009 Rev. *D
191