EP7312_05 Datasheet, PDF (8/64 Pages) Cirrus Logic – High-performance, Low-power, System-on-chip with SDRAM & Enhanced with SDRAM & Enhanced

EP7312
High-Performance, Low-Power System on Chip
CODEC Interface
The EP7312 includes an interface to telephony-type CODECs
for easy integration into voice-over-IP and other voice
communications systems. The CODEC interface is
multiplexed to the same pins as the DAI and SSI2. Table 6
shows the CODEC Interface Pin Assignments.
Table 6. CODEC Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
PCMCLK
PCMOUT
PCMIN
PCMSYNC
O
Serial bit clock
O
Serial data out
I
Serial data in
O
Frame sync
Note: See Table 18 on page 11 for information on pin
multiplexes.
SSI2 Interface
An additional SPI/Microwire1-compatible interface is
available for both master and slave mode communications. The
SSI2 unit shares the same pins as the DAI and CODEC
interfaces through a multiplexer. The SSI2 Interface has these
features:
• Synchronous clock speeds of up to 512 kHz
• Separate 16 entry TX and RX half-word wide FIFOs
• Half empty/full interrupts for FIFOs
• Separate RX and TX frame sync signals for asymmetric
traffic
Table 7 shows the SSI2 Interface pin assignments.
Table 7. SSI2 Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
SSICLK
SSITXDA
SSIRXDA
SSITXFR
SSIRXFR
I/O Serial bit clock
O
Serial data out
I
Serial data in
I/O Transmit frame sync
I/O Receive frame sync
Note: See Table 18 on page 11 for information on pin
multiplexes.
Synchronous Serial Interface
The EP7312 Synchronous Serial Interface has these features:
• ADC (SSI) Interface: Master mode only; SPI and
Microwire1-compatible (128 kbps operation)
• Selectable serial clock polarity
Table 8 shows the Synchronous Serial Interface pin
assignments.
Table 8. Serial Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
ADCLK
ADCIN
ADCOUT
nADCCS
SMPCLK
O
SSI1 ADC serial clock
I
SSI1 ADC serial input
O
SSI1 ADC serial output
O
SSI1 ADC chip select
O
SSI1 ADC sample clock
LCD Controller
A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The display
frame buffer start address is programmable, allowing the LCD
frame buffer to be in SDRAM, internal SRAM or external
SRAM. The LCD controller has these features:
• Interfaces directly to a single-scan panel monochrome STN
LCD
• Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
• Panel width size is programmable from 32 to 1024 pixels in
16-pixel increments
• Video frame buffer size programmable up to
128 KB
• Bits per pixel of 1, 2, or 4 bits
Table 9 shows the LCD Interface pin assignments.
Table 9. LCD Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
CL1
CL2
DD[3:0]
FRM
M
O
LCD line clock
O
LCD pixel clock out
O
LCD serial display data bus
O
LCD frame synchronization pulse
O
LCD AC bias drive
64-Key Keypad Interface
Matrix keyboards and keypads can be easily read by the
EP7312. A dedicated 8-bit column driver output generates
8
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
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