EP7312_05 Datasheet, PDF (51/64 Pages) Cirrus Logic – High-performance, Low-power, System-on-chip with SDRAM & Enhanced with SDRAM & Enhanced

Ball Location
F13
F14
F15
F16
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
J1
J2
J3
J4
J5
J6
DS508F1
Name
nBATCHG
VSSIO
D[11]
VDDIO
PB[1]
VDDIO
TDO
PB[4]
PB[6]
VSSCore
VSSRTC
DD[0]
D[3]
VSSRTC
A[7]
A[8]
A[9]
VSSIO
D[12]
D[13]
PA[7]
PA[5]
VSSIO
PA[4]
PA[6]
PB[0]
PB[2]
VSSRTC
VSSRTC
A[10]
A[11]
A[12]
A[13]/DRA[14]
VSSIO
D[14]
D[15]
PA[3]
PA[1]
VSSIO
PA[2]
PA[0]
TXD[1]
EP7312
High-Performance, Low-Power System on Chip
Table 22. 256-Ball PBGA Ball Listing (Continued)
Strength^†
Reset
State
1
Low
1
Input^‡
1
‡
Input
1
‡
Input
1
‡
Input
1
Low
1
Low
1
Low
1
Low
1
Low
1
Low
1
Low
1
‡
Input
1
‡
Input
1
Input^‡
1
Input^‡
1
‡
Input
1
‡
Input
1
Low
1
Low
1
Low
1
Low
1
Low
1
Low
1
‡
Input
1
‡
Input
1
Input^‡
1
Input^‡
1
High
Type
I
Pad ground
I/O
Pad power
I
Pad power
O
I
I
Core ground
RTC ground
O
I/O
RTC ground
O
O
O
Pad ground
I/O
I/O
I/O
I/O
Pad ground
I/O
I/O
I/O
I/O
RTC ground
RTC ground
O
O
O
O
Pad ground
I/O
I/O
I/O
I/O
Pad ground
I/O
I/O
O
Description
Battery changed sense input
I/O ground
Data I/O
Digital I/O power, 3.3V
GPIO port B
Digital I/O power, 3.3V
JTAG data out
GPIO port B
GPIO port B
Core ground
Real time clock ground
LCD serial display data
Data I/O
Real time clock ground
System byte address
System byte address
System byte address
I/O ground
Data I/O
Data I/O
GPIO port A
GPIO port A
I/O ground
GPIO port A
GPIO port A
GPIO port B
GPIO port B
Real time clock ground
Real time clock ground
System byte address
System byte address
System byte address
System byte address / SDRAM address
I/O ground
Data I/O
Data I/O
GPIO port A
GPIO port A
I/O ground
GPIO port A
GPIO port A
UART 1 transmit data out
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
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