EP7312_05 Datasheet, PDF(20/64 Page) Cirrus Logic – High-performance, Low-power, System-on-chip with SDRAM & Enhanced with SDRAM & Enhanced

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EP7312_05 Datasheet, PDF (20/64 Pages) Cirrus Logic – High-performance, Low-power, System-on-chip with SDRAM & Enhanced with SDRAM & Enhanced

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EP7312

High-Performance, Low-Power System on Chip

SDRAM Refresh Cycle

SDCLK

SDCS

tCSa

tCSd

SDRAS

SDCAS

tRAa

tRAd

tCAa

tCAd

SDATA

ADDR

SDQM

[3:0]

SDMWE

Figure 6. SDRAM Refresh Cycle Timing Measurement

Note:

1. Timings are shown with CAS latency = 2

2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.

Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal

DS508F1

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